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MTD6N20E
Preferred Device
Power MOSFET 6 Amps, 200 Volts
N-Channel DPAK
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
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6 AMPERES, 200 VOLTS RDS(on) = 460 mW
N-Channel D
* Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a * * *
Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Pb-Free Package is Available*
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 MW) Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 ms) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG = 25 W) Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1) - Junction-to-Ambient (Note 2) Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 200 200 20 40 6.0 3.8 18 50 0.4 1.75 -55 to 150 54 Unit Vdc Vdc Vdc Vpk Adc Apk W W/C W C mJ 1 2 3 123 Gate Drain Source Device Code = Year = Work Week = Pb-Free Package 4 DPAK CASE 369D STYLE 2 4 Drain YWW 6 N20E 12 3 1 Gate 2 Drain 3 Source 4 DPAK CASE 369C STYLE 2 G S
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
MARKING DIAGRAMS
4 Drain YWW 6 N20EG
TJ, Tstg EAS
RqJC RqJA RqJA
2.50 100 71.4
C/W
Maximum Temperature for Soldering TL 260 C Purposes, 1/8 from case for 10 secs ORDERING INFORMATION Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not See detailed ordering and shipping information in the package normal operating conditions) and are not valid simultaneously. If these limits are dimensions section on page 7 of this data sheet. exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Preferred devices are recommended choices for future use 1. When surface mounted to an FR4 board using the minimum recommended and best overall value. pad size. 2. When surface mounted to an FR4 board using the 0.5 sq. in. drain pad size. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
6N20E Y WW G
(c) Semiconductor Components Industries, LLC, 2005
1
August, 2005 - Rev. 3
Publication Order Number: MTD6N20E/D
MTD6N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 6.0 Adc) (ID = 3.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 160 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 6.0 Adc, VGS = 10 Vdc, RG = 9.1 W) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 3) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD - - trr (IS = 6.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperature. LD LS - - 4.5 7.5 - - nH nH ta tb QRR - - - - 0.99 0.9 138 93 45 0.74 1.2 - - - - - mC ns Vdc - - - - - - - - 8.8 29 22 20 13.7 2.7 7.1 5.9 17.6 58 44 40.8 21 - - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 342 92 27 480 130 55 pF VGS(th) 2.0 - RDS(on) VDS(on) - - gFS 1.5 2.9 - - 5.0 4.4 - mhos - 3.0 7.1 0.46 4.0 - 0.700 Vdc mV/C Ohm Vdc V(BR)DSS 200 - IDSS - - IGSS - - - - 10 100 100 nAdc - 689 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
Reverse Recovery Time (See Figure 14)
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MTD6N20E
TYPICAL ELECTRICAL CHARACTERISTICS
12 TJ = 25C I D , DRAIN CURRENT (AMPS) 10 8 6 4 2 0 6V 12 I D , DRAIN CURRENT (AMPS) 10 8 6 4 2 0
VGS = 10 V
9V 8V 7V
VDS 10 V
TJ = -55C 25C 100C
5V 0 1 2 3 4 5 6 7 8 9
2
3
4
5
6
7
8
9
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
1.2 VGS = 10 V 1.0 0.8 0.6 0.4 0.2 0 TJ = 100C
0.70 TJ = 25C 0.65 0.60 0.55 0.50 0.45 0.40 15 V
25C -55 C
VGS = 10 V
0
2
4
6
8
10
12
0
2
4
6
8
10
12
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2.5 2.0 VGS = 10 V ID = 3 A I DSS , LEAKAGE (nA)
100 VGS = 0 V TJ = 125C
100C 10
1.5
1.0
0.5
25C
0 - 50
- 25
0
25
50
75
100
125
150
1
0
50
100
150
200
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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MTD6N20E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
900 750 C, CAPACITANCE (pF) 600 450 300 Coss 150 0 Crss 10 5 VGS 0 VDS 5 10 15 20 25 Ciss Ciss VDS = 0 V VGS = 0 V
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
TJ = 25C
Crss
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTD6N20E
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 Q3 0 2 4 VDS 6 8 10 QT, TOTAL CHARGE (nC) 12 Q1 Q2 VGS 60 45 30 15 0 14 75 90 1000 VDD = 100 V ID = 6 A VGS = 10 V TJ = 25C
100
tr td(off) 10 td(on)
tf
ID = 6 A TJ = 25C
1
1
10 RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
6 I S , SOURCE CURRENT (AMPS) 5 4 3 2 1 0 VGS = 0 V TJ = 25C
0.5
0.6 0.7 0.8 0.9 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1.0
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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MTD6N20E
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 60 E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) 50 40 30 20 10 0
VGS = 20 V SINGLE PULSE TC = 25C 10 ms 100 ms
ID = 6 A
10
1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
1 ms 10 ms dc 1000
0.1 0.1
1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
25
50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)
150
Figure 11. Maximum Rated Forward Biased Safe Operating Area
1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
P(pk)
t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01
t1
RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t) 1.0E+00 1.0E+01
0.01 1.0E-05
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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MTD6N20E
ORDERING INFORMATION
Device MTD6N20E MTD6N20E1 MTD6N20ET4 MTD6N20ET4G Package DPAK DPAK Straight Lead DPAK DPAK (Pb-Free) Shipping 75 Units / Rail 75 Units / Rail 2500 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MTD6N20E
PACKAGE DIMENSIONS
DPAK CASE 369C-01 ISSUE O
-T- B V R
4
SEATING PLANE INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 ---
C E
DIM A B C D E F G H J K L R S U V Z
A S
1 2 3
Z U
K F L D G
2 PL
J H 0.13 (0.005) T
M
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
SOLDERING FOOTPRINT*
6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MTD6N20E
PACKAGE DIMENSIONS
DPAK CASE 369D-01 ISSUE B
B V R
4
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ---
Z A
3
S -T-
SEATING PLANE
1
2
K
F D G
3 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K R S V Z
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MTD6N20E/D

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